| Name | Version | Summary | date |
|---|---|---|---|
| peakrdl-python | 0.7.4 | Generate Python Register Access Layer (RAL) from SystemRDL | 2024-04-02 13:26:09 |
| peakrdl-regblock | 0.22.0 | Compile SystemRDL into a SystemVerilog control/status register (CSR) block | 2024-04-01 05:27:07 |
| peakrdl-ipxact | 3.4.4 | Import and export IP-XACT XML to/from the systemrdl-compiler register model | 2024-03-30 06:04:08 |
| hour | day | week | total |
|---|---|---|---|
| 76 | 1632 | 9461 | 204145 |